LAB 3 component
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code
ส่วน comp
library ieee,work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comp is
port(
CLK ,PB ,RST_B : in std_logic;
data : out std_logic
);
end comp ;
architecture behave of comp is
signal out0 :std_logic;
signal out1 : std_logic_vector(0 to 23);
component push
port( CLK ,PB : in std_logic;
OUTPB : out std_logic
);
end component;
component state
port( CLK ,checkPB ,RST_B : in std_logic;
OUTREG : out std_logic_vector(0 to 23)
);
end component;
component outState
port( CLK : in std_logic;
REGin : std_logic_vector(0 to 23);
data : out std_logic
);
end component;
begin
U0:push port map(CLK,PB, out0);
U1:state port map(CLK ,out0 ,RST_B, out1 );
U2:outState port map(CLK, out1 ,data);
end behave;
ส่วน push
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity push is
port(
CLK ,PB : in std_logic;
OUTPB : out std_logic
);
end push ;
architecture behave of push is
signal Index ,countIndex,countGab : integer := 0;
signal SETPB,check : std_logic;
signal REG : std_logic_vector(23 downto 0) := x"000000";
begin
process(CLK,PB) begin
if rising_edge(CLK) then
SETPB <= '0';
if PB = '0' then
check <= '1';
else
if PB = '1' and check = '1' then
SETPB <= '1';
end if;
check <= '0';
end if;
end if;
end process;
OUTPB <= SETPB ;
end behave;
ส่วน state
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity state is
port(
CLK ,checkPB ,RST_B: in std_logic;
OUTREG : out std_logic_vector(23 downto 0) := x"000000"
);
end state ;
architecture behave of state is
signal Index ,countIndex,countGab : integer := 0;
signal check, outPWM : std_logic;
signal REG : std_logic_vector(23 downto 0) := x"000000";
begin
process(CLK,RST_B) begin
if RST_B = '0' then
REG <= x"000000";
index <= 0;
check <= '0';
countIndex <= 0;
elsif rising_edge(CLK) then
if checkPB = '1' then
if REG = x"000000" then
REG <= x"0000FF";
elsif REG = x"0000FF" then
REG <= x"00FF00";
elsif REG = x"00FF00" then
REG <= x"FF0000";
elsif REG = x"FF0000" then
REG <= x"000000";
end if;
end if;
end if;
end process;
OUTREG <= REG ;
end behave;
ส่วน outState
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity outState is
port(
CLK : in std_logic;
REGin : in std_logic_vector(23 downto 0) := x"000000";
data : out std_logic
);
end outState ;
architecture behave of outState is
signal Index ,countIndex,countGab : integer := 0;
signal check, outPWM : std_logic;
constant T0H : integer := 18;
constant T0L : integer := 57;
constant T1H : integer := 35;
constant T1L : integer := 65;
type state_type is (S0,S1,S2);
signal state : state_type := S0;
begin
process(CLK) begin
case state is
when S0 =>
if Index = 24 then
if countGab < 1000 then
countGab <= countGab + 1;
else
countIndex <= 0;
Index <= 0;
countGab <= 0;
end if;
data <= '0';
else
if REGin(Index) = '0' then
state <= S1;
else
state <= S2;
end if;
--Index <= Index +1 ;
end if;
when S1 =>
if countIndex <= T0H then
data <= '1';
countIndex <= countIndex + 1;
elsif countIndex > T0H and countIndex <= T0L then
data <= '0';
countIndex <= countIndex+1;
elsif countIndex > T0L then
Index <= Index + 1;
countIndex <= 0;
end if;
state <= S0;
when S2 =>
if countIndex <= T1H then
data <= '1';
countIndex <= countIndex + 1;
elsif countIndex > T1H and countIndex <= T1L then
data <= '0';
countIndex <= countIndex + 1;
elsif countIndex > T1L then
Index <= Index + 1;
countIndex <= 0;
end if;
state <= S0;
end case;
end process;
end behave;
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